TRISHULCORE SEMICONDUCTORS PRIVATE LIMITED

In their own words

Innovation: Legacy chips use shared-bus architectures vulnerable to quantum attacks. TrishulCore is developing "Sovereign TPM 2.0," a FIPS 140-3 Level 3 Hardware Security Module. Our patented "Split-Bus Topology" physically isolates the cryptographic core to an integrated secure memory, creating an impenetrable firewall. To address the NIST 2030 mandate, our Universal PQC Socket is engineered to permanently integrate Lattice-Based Post-Quantum Cryptography into the RTL, via a planned collaboration with IIT Kanpur (C3iHub). A proprietary Known Answer Test (KAT) multiplexer provides an immutable, zero-intervention hardware kill-switch. Scalability: Targeting the indigenous SCL Mohali 180nm CMOS node ensures microscopic die sizes (~65k gates) and highly cost-effective wafer yields. Our "Hardware-Software Co-Design" accelerates scalability: we collaborate with domestic OEMs (defense, 5G) to hardcode specific motherboard SPI wait-states into our RTL before tape-out, eliminating integration friction. Operating as a drop-in "Merchant Silicon" SPI slave, it allows Indian infrastructure to immediately achieve "Trusted Source" compliance. This severs reliance on foreign silicon, establishing a domestic monopoly and positioning India as an exporter of quantum-resilient defense silicon.

Written by the company on its public Startup India profile. Not verified by us.